Online program Overview Session: NSS-20

Abstract

We present the development and validation of the Forward Feature Extractor (fFEX) prototype module, a key component of the ATLAS Experiment’s Phase-II Level-0 Calorimeter (L0Calo) trigger system for real-time event filtering and feature extraction. The prototype module has been produced and validated through an extensive test campaign. Hardware validation demonstrates stable power delivery, full main-board core functionality, reliable FPGA operation including high-speed transceivers and bit-error-rate tests at 25.8 Gbps per link, robust clock distribution including jitter cleaners and fanout stages, and complete control and monitoring functionality. In addition, integration tests with other ATLAS Phase-II subsystems have been carried out and the results are reported, confirming interoperability and being suitable for operation within the experiment’s complex trigger and data-acquisition architecture. The system achieves a total throughput of 2.5 Tbps per main FPGA, including real-time processing and data-handling operations. On the firmware side, a modular design has been implemented, comprising the infrastructure layer, including an implementation of the Interlaken protocol (Core1990) and a simple-packet based protocol called IPBus, the readout firmware, and the algorithmic firmware. In this article, particular emphasis is placed on the readout path and the handling of multiple data types and trigger objects, including the formatting, error-correction and flow-control aspects. The algorithmic firmware supports the identification of jets, electromagnetic clusters, and hadronic tau candidates, and the calculation of global quantities such as missing transverse energy (MET). These results demonstrate the technical readiness of the fFEX prototype for further system-level integration, timing and performance studies.

Abstract

The sPHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), and RHIC itself, concluded their beam operations on Feb. 6, 2026. RHIC and the experiments are now being decommissioned to begin construction of the Electron-Ion Collider. This marks the end of 25 years of Heavy-Ion and polarized proton-proton Physics at the facility.

sPHENIX was designed as a high-rate detector optimized for precision measurements of jets, heavy flavor, and quarkonia in Relativistic Heavy-Ion collisions. Following a successful commissioning phase, the experiment collected high-quality data in p-p , Au-Au, and O-O collision systems.

To summarize our key performance numbers:

• The sPHENIX DAQ system has exceeded the design event rate of 15 kHz
• We were able to sustain a DAQ data rate of more than 70 GB/s
• We accumulated just under 300 PB of data on tape with beam, and crossed the 300 PB threshold with the post-shutdown calibration data.

Abstract

This work presents the development and validation of a Trigger, Tracking, and Readout System for the beam test characterization of novel particle detectors, designed to address the challenges of providing precise reference tracking for event reconstruction while integrating heterogeneous front-end electronics. The system combines a scalable tracking apparatus based on scintillating fibers coupled to Silicon Photomultipliers, a Centralized Control Unit for trigger generation and system synchronization and a modular readout architecture based on Field Programmable Gate Arrays. A dedicated software platform provides unified control of data acquisition, configuration and monitoring, ensuring efficient system operation. The overall design approach relies on hardware modularity and the use of commercial components, complemented by adaptable firmware and software to interface multiple detector technologies with minimal customization effort. The system has been validated during beam test campaigns of a Ring Imaging Cherenkov detector prototype for the future ALICE3 experiment, foreseen at the High-Luminosity Large Hadron Collider. The results demonstrate accurate event reconstruction capability, with a data matching efficiency among independent readout boards exceeding 99%, ensuring reliable synchronization across different subsystems. In addition, a time resolution at the level of a few tens of picoseconds have been measured, highlighting the remarkable timing performance of the system and its suitability for the characterization of high-precision timing detectors. The results confirm the effectiveness of the proposed system as a cost-effective, flexible, scalable, and portable solution that can be readily employed for the development and beam test validation of future particle detectors based on a wide range of technologies.

Abstract

TD-Link is a versatile optical communication architecture combining high-throughput data readout and sub-nanosecond timing synchronization over a single optical fiber for large-scale detector systems. The protocol adopts a multidrop daisy-chain ring topology connecting one Data Concentrator to up to sixteen FERS front-end boards per link, with multiple independent links per concentrator, enabling scalable instrumentation with reduced optical infrastructure. Operating at 3.25 Gb/s, TD-Link transports data, synchronization, and control traffic within the same serial stream through a token-based protocol minimizing per-hop latency and supporting packet fragmentation.
The synchronization system distributes a global time reference (T0) with deterministic latency. On the concentrator, transmitter lane alignment exploits the half-full condition of the transceiver elastic buffer as a 1-bit phase detector. A firmware state machine iteratively adjusts the TX phase interpolator until the write-to-read pointer difference reaches half the buffer depth, locking the lane to a deterministic phase condition. A Digital Dual Mixer Time Difference (DDMTD) circuit is used only for inter-concentrator synchronization, compensating the phase offset between the recovered transceiver clock and the FPGA fabric reference clock.
On FERS boards, recovered clocks are cleaned through an external zero-delay PLL and retransmitted downstream, preserving phase coherence along the daisy chain. Deterministic T0 latency is ensured by disabling elastic buffers and routing timing signals through calibrated delay paths.
Experimental validation with CERN PicoTDC-equipped FERS boards demonstrates a synchronization sigma of 6 ps for boards sharing the same coaxial clock reference and below 25 ps for boards connected to different concentrators. The performance remains stable across repeated power cycles, confirming the robustness of the phase alignment strategy.

Abstract

This paper presents the design of a board named RDO (ReaDOut module) which is the main building block of the readout system for the dual-radiator RICH (dRICH) of the ePIC experiment at the future Electron-Ion Collider (EIC). The main purpose of the board is to provide an interface towards the front-end ASICs (the ALCOR chips) and towards the main data acquisition system (the FELIX boards) through a high-speed optical link based on the CERN VTRx+ optical transceiver. Among the many requirements, the board needs to fit a very limited size and must withstand a moderately hostile radiation environment. The board has already been used in a test-beam at CERN and it has also undergone irradiation tests of its main components: the most significant results will be presented and discussed.

Abstract

The LHCb Phase-II electromagnetic calorimeter upgrade, known as PicoCal, requires new radiation-tolerant front-end electronics capable of providing precise energy and timing measurements under the demanding conditions expected after the High-Luminosity LHC upgrade. Two dedicated ASICs are being developed for this purpose in TSMC65 technology: ICECAL65 for energy measurement, and SPIDER for picosecond timing reconstruction. ICECAL65 follows the scheme in the ASIC currently used in the LHCb calorimeter. Nonetheless, it adopts a dual-gain architecture with time-interleaved subchannels to achieve 12-bit precision over a wide dynamic range while eliminating dead time between input samples. The analog chain integrates configurable shaping, tunable integration, and high-speed track-and-hold stages synchronized through an integrated PLL. Post-layout simulations indicate a power consumption of 40 mW per channel, output noise compatible with 12-bit precision, linearity errors below 1%, and spillover below 2.5%. SPIDER is a waveform digitizer ASIC dedicated to ultra-fast timing measurements. Based on the Waveform Time-to-Digital Converter concept, it samples detector signals inside programmable windows synchronized with the 40 MHz LHC clock. The architecture combines analog memory banks, embedded discriminators, DLL-based timing control, and massively parallel Wilkinson ADC conversion. Configurable sampling frequencies from 1.6 to 20 GS/s enable timing resolutions well below 10 ps rms. While post-layout simulations of ICECAL65 are still pending verification, first measurements of SPIDER_V0 demonstrate a Time Difference Resolution of 7.13 ps rms between two asynchronous pulses, corresponding to a single-channel precision close to 5 ps. Together, ICECAL65 and SPIDER provide a complete front-end solution for the PicoCal upgrade and represent a promising platform for future fast-timing detectors in high-energy physics.

Abstract

We present the design and performance of the FCFD1.1 constant-fraction discriminator ASIC for precision timing detectors based on AC-LGAD sensors. The chip, implemented in 65 nm CMOS, achieves ~ 40 ps time resolution and 15-20 μm spatial resolution in beam tests, with full detection efficiency over the sensor surface. The design integrates on-chip time-walk correction, reducing reliance on offline calibration. Building on this result, we introduce FCFD1.2, a six-channel full-chain prototype for AC-LGAD readout. Each channel includes a constant-fraction discriminator, an ADC block, and a self-calibrated TDC, while the six channels share a common readout block that packs the data into frames and outputs them through a serializer. The chip was submitted in April 2026, and preliminary test results are expected to be presented at the conference. Its architecture targets ~ 45 ps overall timing resolution, with less than 10 ps contribution from the internal electronics, enabling scalable, low-power timing readout for future detector systems.

Abstract

The Light Dark Matter eXperiment (LDMX) will search for sub-GeV dark matter with a fixed-target missing-momentum technique requiring time-aligned detector data from several independent subsystems, including the Trigger Scintillator, Silicon Tracker, Electromagnetic Calorimeter, and Hadronic Calorimeter. This work presents the LDMX trigger and data acquisition (TDAQ) system for timing distribution, fast control, and event tagging. The central timing node is implemented on an APx ATCA board originally developed for CMS. It receives the LCLS-II accelerator timing stream and recovers the 185.714 MHz timing clock and timing frames. Firmware combines accelerator pulse identifiers, run state, and Global Trigger decisions into fixed-latency 3.714 Gbps PGP Fast Control (PGPFC) messages for endpoints. Timing Messages carry a 56-bit pulse ID, 4-bit run state, and state-changed flag. Readout Request (RoR) messages, analogous to Level-1 Accept triggers, carry pulse ID and a 6-bit bunch count. Endpoints recover the fast-control clock, derive a 37.14 MHz bunch clock, align RoRs to bunch boundaries, and write the common timestamp into DAQ event headers. Common firmware blocks provide fast-control reception and event formatting for subsystem designs, enabling offline alignment and future real-time event building. Run states support trigger-data alignment and RoR-latency calibration before physics. In a 2025 beamline test at End Station A at SLAC, this architecture acquired coherent data at 10 Hz for up to 12 hours with aligned contributions from participating reduced-scale detector-subsystem slices.