Online program Overview Session: NSS-14

Abstract

ToRA is a 64 channel ASIC for the readout of gaseous detectors used in high energy physics experiments. Its driving application is the readout of the MicroMega detectors for the AMBER experiment upgrade. However, it is designed to be highly flexible in order to be used also for other types of gaseous detectors, e.g. straw detectors.
Each ToRA channel provides programmable signal amplification and shaping. The ASIC provides the time measurement of the time of arrival, the time over threshold and the peak position of the shaper signal. Moreover, the peak value is hold and converted with a single ramp ADC.
A fully digital interface, based on differential serial links and including a data and a control interface, has been implemented. The events are packed into 32-bit words and transmitted over two 200 Mb/s links.

Abstract

This work presents an 8-channel ASIC designed in 180 nm CMOS technology for γ-ray spectroscopy as part of the EU-funded project i-RASE. i-RASE aims at developing a novel generation of radiation detectors capable of performing real-time processing by adopting artificial neural networks (ANN) to reconstruct energy, position, and timing of incoming photons. The ASIC is specifically tailored for room temperature detectors, featuring large detector capacitance (up to 50 pF), like CdZnTe. It includes dual-polarity charge sensitive amplifiers (CSA) with pulsed-reset and leakage current compensation (LCC), sample-and-hold circuitry controlled by a digital logic shared among the channels, and both single-ended and differential output architectures. Two readout modes are supported: a continuous mode, compatible with conventional analog and digital readout and shaping chains, and a high-speed sampling mode, in which a switched capacitor array (SCA) continuously samples the analog output of the CSA at frequencies up to 100 MHz. The samples are stored in 256 capacitors and subsequently buffered to an external differential ADC, triggered by the ASIC event thresholds, and controlled by the FPGA running the ANN. The preliminary results of the ASIC characterization (rise time of 100 ns, linearity of 0.5%), performed by injecting test signals, are presented and match simulations.

Abstract

This work presents the design and experimental characterization of a prototype channel developed in a 65 nm CMOS process for the readout of the large-area lithium-drifted silicon detectors of the General Antiparticle Spectrometer tracker. To simultaneously achieve high-resolution X-ray spectroscopy below 100 keV and a wide dynamic range up to 100 MeV, the charge-sensitive amplifier employs a dynamic-threshold MOS feedback capacitor exploiting dynamic signal compression. An enhanced Krummenacher network provides continuous feedback discharge, compensating detector leakage currents up to 200 nA. Experimental results demonstrate an energy resolution of 3.2 keV full width at half maximum (379 e⁻ rms equivalent noise charge) and an integral nonlinearity below 1.5%. A compensation technique to mitigate temperature-induced variations in the charge-sensitive amplifier response is also presented.

Abstract

We present the  first measurements for the third revision of the High Pitch digitizer System-on-Chip (HPSoC), a 9 channel Readout Integrated Circuit (ROIC) prototype. The HPSoC concept is that of a high channel density and scalable  waveform digitization ROIC  with an embedded interface to advanced high-speed sensor arrays such as e.g. AC-LGADs. The chip was fabricated in 65nm technology and targets  picosecond-level timing resolution via high speed waveform sampling (in excess of 10 Gsps), autonomous chip triggering and feature extraction. In this paper, we present the results of testing of the chip’s   timing generation and digitization.

Abstract

The LEGEND (Large Enriched Germanium Exper iment for Neutrinoless double beta Decay) experiment aims to detect neutrinoless double beta decay (0νββ) in 76Ge using large scale cryogenic germanium detectors. A 0.35µm LUIGI ASIC was designed as a detector readout, ensuring low noise and high radiopurity conditions. Such front-end ASIC, when assembled to the Ge detector, must operate at cryogenic temperatures, typically 87 K using liquid argon (LAr). At cryogenic temperatures, semiconductor characteristics shift significantly, while standard transistor models, typically validated only to −55◦C (218.15 K), become inaccurate. therefore, this work presents a workflow for cryogenic MOSFET modeling based on BSIM4, using experimen tal data measured at 77 K. The model is extracted from mea surements at both room and cryogenic temperatures, validated with corresponding Cadence models at room temperature, and is then used to assess the impact of cryogenic effects on analog circuit performance. Further experimental characterization on a new set of transistors will be made is required to refine and improve the accuracy of the model.

Abstract

On-chip thermometry is vital in cryogenic circuit systems implemented in the temperature of liquid nitrogen or even liquid helium, such as superconducting cubit controllers and astronomical detectors. As transistor density increases, the power consumption of the chip may induce localized overheating, leading to device failure. Typical CMOS temperature sensors can be mainly categorized as BJT-based, resistor-based, and MOSFET-based. Most of them are unable to work below 50 K, which is necessary for deployment in superconducting quantum control systems. Meanwhile, experiments have shown that the threshold voltage of a PMOS transistor exhibits a linear temperature dependence due to the Fermi potential, and this PTAT characteristic becomes even more sensitive as the temperature decreases into the deep-cryogenic region. In this paper, we present a deep cryogenic CMOS temperature sensor based on the threshold voltage of a PMOS transistor. We use a threshold voltage extractor circuit to monitor the targeted transistor and output its threshold voltage. Then the threshold voltage is transformed into current and fed into a integrator that operates on a capacitor charge–discharge cycle, producing a square-wave signal whose frequency is temperature-dependent. Subsequently, a counter is used to digitize the temperature by measuring this frequency. This article describes a deep cryogenic temperature sensor in 28-nm CMOS technology with an area of 0.05 mm². With an output resolution of 0.1 K from 233 K to 398 K, it consumes 48.1 µW at 1.8 V at  233 K.

Abstract

X-ray fluorescence analysis is a fast, non-destructive technique for material characterization and recycling, where silicon drift detector-based systems provide high energy resolution. Portable applications require a high integration density, while conventional state of the art solutions depend on external highvoltage electronics occupying more than 250 mm². To address this challenge, this work presents an application-specific integrated
circuit fabricated in 180 nm silicon-on-insulator technology that generates all negative high voltages required for silicon drift detector operation in the range from -20 V to -130 V. Each voltage supply is implemented using a CMOS DC/DC converter based on a Pelliconi charge pump. The employed topology utilizes low-voltage transistors and a simple two-phase clock scheme driven by a ring oscillator at 10 MHz, enabling high efficiency while reducing chip area. The stability, noise, and spectral performance of a silicon drift detector operated with the proposed charge-pump-based supply is compared to those obtained with a conventional power supply. The results show that operation of a silicon drift detector module using an external ASIC-based charge pump is possible with high energy resolution for peaking times exceeding 1 μs, provided that the generated voltages are sufficiently smoothed using external capacitors. These results facilitate the development of more compact and cost-effective silicon drift detector power supply solutions.

Abstract

The Analog Spectral Imager for X-rays (ASIX) is a technology demonstrator for a Hybrid Pixel Detector (HPD) aimed at delivering high-resolution measurements in both spatial and energy domains, thus enabling advanced X-ray spectral imaging. ASIX features 50~$\mu$m pixels arranged into a hexagonal array. An in-pixel ultra-low noise front-end (<30 ENC at Cd=100 fF), together with a self-triggering logic, and a highly segmented readout, enables precise identification of the charge clusters on a photon-by-photon basis.
The readout architecture is based on regions. Each region comprises a 16 X 8 pixel matrix and dedicated readout electronics including a compact 10-bit SAR ADC, a data-out FIFO and the readout-controller sequencing logic. The full demonstrator chip will be composed of a 6 X 12 array of regions, corresponding to a 96 X 96 pixel matrix, together with a digital output logic responsible for collecting, formatting and serializing data.
We developed a 2 X 2 mm^2 prototype readout chip in a commercial 65 nm CMOS process featuring a fully functional region. 
Given its 4-side abuttable layout and its almost exclusively digital interfaces, this can be regarded as the main building block for readout matrices in larger-scale ASICs such as the future full-scale demonstrator.