Online program Overview Session: NSS-23

Abstract

We present a CMOS-based QUBO solver ASIC architecture and its application to charged particle track reconstruction for high-energy physics. The solver implements a fully parallel spin-update engine operating on the Ising Hamiltonian Y = −(SUMij si Jij sj − Hi si) with 8-bit fixed-point coupling interaction coefficients, which gets mapped to Quadratic Unconstrained Binary Optimization(QUBO) problems via the standard spin-to-binary substitution xi = (si + 1)/2. The QUBO encodes track-finding physics through diagonal terms (geometric edge quality) and off-diagonal terms (triplet collinearity rewards and bifurcation penalties) derived from the Denby-Peterson formulation. The solver is evaluated as a front-end edge discriminator in a two-stage track reconstruction pipeline on TrackML simulated data. Unlike prior quantum annealing-inspired approaches that rely on a Gaussian KDE trained on ground-truth edge features, our method requires no supervised training or labeled-edge fitting — edge quality is determined entirely by the solver’s combinatorial optimization over local neighborhoods. The pipeline achieves F1 = 84.1% (precision 89.3%, recall 79.6%), within 4% of the KDE-dependent baseline while exceeding it in precision.

Abstract

The detector of TRopIcal DEep-sea Neutrino Telescope (TRIDENT) will use large-area silicon photomultiplier (SiPM) arrays combined with photomultiplier tubes to boost photon detection efficiency and pointing capability. An application-specific integrated circuit (ASIC) is being developed to aim at high-resolution time measurement of large-area SiPM arrays. 16 front-end channels are embedded in the ASIC, with output logical-ORed on LVDS output to interface external TDC. Each channel includes a front-end buffer and a discriminator, both in current mode for higher bandwidth while reducing power. To compensate for inconsistency of propagation delay due to detector array layout and process variation, a programmable delay line is introduced for each channel. The delay line consists of coarse and fine delay cells with 165 ps and 33 ps resolution respectively and a dynamic range of 3000 ps. When connected to 16 2s2p SiPM (Hamamatsu S13360-3050PE) arrays with a total area of 5.76 cm², the system achieved a timing jitter of <500 ps FWHM.

Abstract

BaF₂ emits a prompt fast component with a sub-nanosecond decay time (~0.6 ns), ideal for ultrafast timing applications. Previous studies proved discriminated fast-component-dominant events based on pulse amplitude and slew rate characteristics could improve coincidence time resolution (CTR) in BaF₂. In this work, the fast-component discrimination method was implemented using FPGA-based dual-threshold time-over-threshold (DTOT) readout circuit, providing scalable architecture for multi-channel systems.

To reproduce the pulse amplitude and slew-rate characteristics used in previous full-waveform analysis using oscilloscope, the proposed DTOT method extracted amplitude-related, slew-rate-related parameters using two voltage thresholds applied to the pulse. Low-threshold TOT width provided amplitude-correlated parameter, while the timing difference between low- and high-threshold crossings provided pulse slew rate. Because fast-component-dominant events exhibited steeper rising edges, these parameters enabled fast-component discrimination without full waveform sampling.

The FPGA-based DTOT readout circuit consisted of BaF₂ coupled to VUV-MPPC SiPM, two-stage high frequency amplifier designed to provide sufficient gain with preserving rising-edge profile of fast component, low-latency comparators for accurate slew-rate extraction, and FPGA-based TDC for timestamping threshold crossings.

Abstract

As chip design costs and complexity rises, the industry is increasingly shifting toward application versatility. The digital readout of the PoETIC chip, designed for custom Silicon Photomultiplier (SiPM) detectors within the PetVision project, embodies this philosophy, supporting Positron Emission Tomography (PET), mass spectrometry, and other high- precision low-rate (≤1 MHz) Time-of-Flight (ToF) applications. The architecture has 16 channels, with three thresholds each: (1) ≤1 photon Low Threshold (ThL), (2) a few-photons High Threshold (ThH), and (3) above ten photons Trigger Threshold (ThT). ThL and ThH are connected to dedicated Time-to-Digital Converters (TDCs), while the ThT signals are ORed into two groups of eight channels, connected to a separate TDC channel. Each TDC channel provides a ToF of 24.4ps time-bin and a Time-over-Threshold (ToT) of 390ps. Each channel integrates a track-and-hold circuit connected to an ADC for linear energy measurements. To optimize data transmission across diverse applications, the readout supports multiple operational modes and configurations. In low-bandwidth setups, several PoETIC chips can be daisy-chained to share a single communication link, reducing the required system resources. For data compression, a trigger operation mode reduces the data volume by transmitting a full bit-width reference ToF timestamp grouped with delta- encoded timestamps of other hits. For systems requiring external validation, the TDC digitizes the trigger validation signal generated by an external coincidence system so that only validated trigger events are transmitted. A data-driven operation mode allows the transmission of all hits in independent packets. The chip also offers control over ToF, non-linear energy measurement (ToT), and linear energy measurement data, allowing users to configure which information is sent, bit widths, and filtering to balance precision and bandwidth according to the specific requirements of the target application.

Abstract

Analog neural networks (ANN) are promising solutions for achieving fast and efficient data processing, usually trading-off accuracy for ultra-low power operation. For instance, in scintillator-based PET and SPECT gamma cameras, analog processing embedded in the analog acquisition chain can simplify the system design, reducing throughput, power consumption and scanner cost. After a first proof-of-concept, last year we proposed the design of a more advanced version of an Analog Neural Network ASIC (ANNA). We now present the preliminary experimental results of this ANNAv2 chip, fabricated in 110 nm CMOS technology. It features a fully analog charge-domain processing architecture enabling the implementation of configurable feedforward fully connected ANN. Each neuron consists of an efficient inverter-based charge integrator. Thanks to this programmability, its employment is not limited to emission tomography, but can be tailored to other scenarios in processing signals of "intelligent" detectors. The maximum supported complexity is 70 analog inputs with 5 weighted layers, up to 32 neurons per layer, and 32 analog outputs. Weights are quantized over 63 analog levels, with programmable non-linear activation functions. Preliminary measurements performed on the ASIC validate the correct operation of the proposed architecture and demonstrate the feasibility of fully analog end-to-end inference (with an energy cost of 2nJ/inference) for sensor front-end applications.

Abstract

Embedded FPGAs (eFPGAs) combine the performance and efficiency of custom silicon with the flexibility of programmable logic as reconfigurable digital logic can directly be integrated into ASICs. When designed with radiation tolerance techniques such as Triple Modular Redundancy (TMR), eFPGAs can support fault-tolerant and intelligent front-end processing. This enables systems to adapt to evolving data handling needs and environmental conditions, while also supporting local data reduction to lower cabling, power and backend processing demands. Building on previous prototype developments in 130nm and 28nm at SLAC, this paper details the ASIC development of a radiation-hardened eFPGA in 28nm CMOS using radiation-mitigation techniques to realize a reconfigurable logic fabric capable of reliable operation under fault-inducing conditions.