Online program Overview Session: NSS-10

Abstract

We present NSX1, a very-low-power 64-channel front-end ASIC developed for large-area broadband-energy X-ray Silicon Drift Detectors (SDD) for space applications. Fabricated in 180 nm CMOS, it integrates dual-gain charge amplification, shaping, discrimination, peak detection, analog multiplexing, and 12-bit analog-to-digital conversion. The ASIC offers extensive programmability, including high-resolution mode, various discrimination modes, neighbor-channel/chip processing, peak processing modes, and power-down options. At less than 600 µW per channel and ∼110 fF input capacitance (SDD anode + wirebond), it achieves an Equivalent Noise Charge (ENC) below 7 e⁻ (< 6 e⁻ in high-resolution mode), meeting or exceeding STROBE-X requirements.

Abstract

The Continuous Readout Digitizing Imager Array (CoRDIA) is an X-ray hybrid pixel detector currently being developed for scientific experiments exploiting the performance of 4^th generation light sources, in particular that of PETRA IV, but also CW free electron lasers (FELs). Operating on the charge-integrating principle, it adopts the dynamic gain switching architecture and circuit topology of the AGIPD detector at the European XFEL to combine single photon sensitivity with a large dynamic range. Implementing the readout ASIC in a 65 nm CMOS technology enables a small pixel size of 110 × 110 µm².
To ensure up to 150 kframes/s dead time free operation, images are stored by a sample and hold (S&H) circuit, before digitisation by an 11 bit SAR ADC serving blocks of 16 pixels each. Data from 128 ADCs (2 kpixels) is driven off-chip by a 5.12 Gbit/s wire transmitter (GWT).
In spring of 2026 we completed the design of the ’20 k’ prototype CoRDIA 0.5, which combines the full signal chain consisting of 1232 4 × 4 pixel blocks (tested on CoRDIA 0.2) with 14 GWTs (tested on Timepix4 and CoRDIA 0.3). This chip also contains a programmable sequencer, controlling the ADC and readout operation. This sequencer is based on an SRAM memory and thus much more flexible than counter-based solutions as implemented e.g. on the AGIPD chip.
In addition to wirebond pads through silicon via (TSV) landing pads are evenly distributed across the whole chip area enabling ’local powering’ for future gapless detectors.
We will present the design of CoRDIA 0.5 with emphasis on the implementation of the readout sequencer, and new characterisation results.

Abstract

In this article we describe the design of the LGAD Integrated Digitizer (LID) - a readout Integrated circuit that is meant for tight coupling with dense LGAD arrays. The circuit is a multi-channel device that performs internal pre-amplification and self-triggered high rate digitization (10 Gsps) and digital processing. The RoIC is an evolution of previous HPSoC chips[1][2][3], and it features variants of the front end Transimpedance amplifier (TIA) that are capable of handling the higher capacitance of strip detectors. The paper will detail the design and performance of the TIAs, the planned integration with sensors, and the definition and hardware implementation of algorithms using waveforms from multiple channels to extract accurate position and timing information.  Simulation results in the presence of noise show that the system is capable of fine location to within 10 percent of the sensor pitch and up to 9 ps  of timing resolution in the best case.

Abstract

We present the design progress and early test results of SparkPix-S, a charge-integrating readout application specific integrated circuit (ASIC) developed for next-generation X-ray cameras operating at the 1 MHz frame rate of LCLS-II. The SparkPix-S detector is being developed for X-ray Photon Correlation Spectroscopy (XPCS) and Speckle Visibility Spectroscopy (XSVS) experiments, where the inherent sparsity of the data — with average frame occupancies well below 1 % — enables a fundamentally different readout approach compared to conventional full-frame readout ASIC architectures. The pixel front-end architecture combines a charge-integrating front-end, coupled to an in-pixel discriminator to control the sparse readout architecture. 1 MHz operation is achieved through the combination of per-pixel asynchronous sparse readout logic, high-speed CML serial links, and a novel frame-work for sparse readouts named Pix2PGP. The first full-reticle (312 × 384 pixels) prototype has been fabricated in 130 nm CMOS technology. Electrical characterization of the front-end confirms noise performance below 60 electrons r.m.s., enabling single-photon sensitivity for tender X-ray energies. We report on the chip architecture, preliminary measurement results with a silicon sensor bump-bonded to the ASIC, and first results from the sample X-ray source testing with Cd-109 and Am-241, demonstrating the viability of the sparsified readout concept for MHz-rate photon science at free-electron laser facilities.

Abstract

A 10-bit single-slope analog-to-digital converter has been developed in a 110 nm CMOS technology for amplitude measurements in large-area pixel detectors for X-ray imaging. The converter generates the linear ramp and the timestamp in the chip periphery and distributes them to the 256x256 pixels in the chip core for comparison with the local amplitude sample. This approach reduces power dissipation in the chip core and achieves an optimal trade-off between IR-drop effects and front-end noise performance, while preserving the integrity of the analog sample at the pixel level. Although the current detector design targets frame rates in the tens-of-kHz range, the possibility of scaling to higher rates is explored through the implementation of a compression feature that accounts for Poisson noise in the photon signal.

Abstract

The IGNITE project is developing advanced technical solutions in 28-nm CMOS technology for next-generation collider tracking systems, targeting time resolutions below 40 ps RMS while preserving the key constraints of current inner trackers, namely small pixel dimensions (~50 μm pitch) and low power density (1–2 W/cm.).

This contribution presents characterization results for the Ignite64 prototype ASIC, featuring a 64x64-pixel matrix with 55 μm pitch and one TDC per pixel. The chip has been conceived as a test platform for advanced silicon sensor technologies, including 3D sensors, TI-LGADs, and i-LGADs. The Ignite64 adopts a modular architecture that is directly scalable to the final IgnitER ASIC, currently close to submission.

The prototype implements and validates dedicated solutions for accurate power delivery and low-jitter clock distribution, both essential for achieving uniform timing performance across large pixel matrices. Several alternative Analog Front-End architectures have also been integrated and experimentally evaluated to optimize the trade-off among timing performance, power consumption, and Total Ionizing Dose tolerance.

At an input charge of 1 fC and a power consumption of 10 μW per pixel, the measured timing resolution is approximately 20 ps RMS at zero input capacitance, remaining around 35 ps RMS at a typical pixel capacitance of 100 fF. Performance uniformity across the full matrix is well controlled, with an RMS spread of about 5 ps in the distribution of pixel time resolutions, demonstrating the effectiveness of the adopted architectural and powering strategies.

Comprehensive laboratory characterization results are presented for operation both with and without connected sensors. Measurements include tests performed using the integrated pulsing system, radioactive sources, and a dedicated infrared laser setup capable of accurately reproducing the charge deposition profile generated by charged particles in silicon sensors.