NSS-23-03 – Scalable FPGA-Based Dual-Threshold Time-Over-Threshold Readout Circuit for Fast-Component Discrimination in BaF₂ (#3182)
M.H. Son, J. Jung, J.H. Jung, Y. Choi
Session: NSS-23 - Analog and digital circuits III
Date: Thursday, 12 November, 2026, 12:00
Location: ALBÉNIZ & MACHUCA ()